1. Technical Field
The present invention relates to a wiring substrate which has a reinforcement for preventing warpage of a resin wiring substrate.
2. Description of Related Art
In recent years, semiconductor integrated circuit devices (IC chips) used as, for example, microprocessors of computers have greatly advanced in operation speed and functionality. In association with such advancement, the number of terminals tend to increase, and the pitch of terminals tends to become narrower. Generally, a large number of terminals are densely arrayed on the bottom surface of an IC chip. Such a group of terminals are flip-chip-connected to a group of terminals on a motherboard. However, since there is a great difference in the pitch of terminals between the group of terminals on the IC chip and the group of terminals on the motherboard, difficulty is encountered in connecting the IC chip directly onto the motherboard. Thus, usually, the IC chip is mounted on an IC-chip-mounting wiring substrate, thereby yielding a semiconductor package. Then, the semiconductor package is mounted on the motherboard (refer to, for example, Japanese Patent Application Laid-open (kokai) No. 2002-26500 (FIG. 1, etc.).
An IC chip is generally formed from a semiconductor material (for example, silicon) having a thermal expansion coefficient of about 2.0 ppm/° C. to 5.0 ppm/° C. By contrast, in many cases, an IC-chip-mounting wiring substrate is a resin wiring substrate, which is formed from a resin material or the like whose thermal expansion coefficient is considerably higher than that of the semiconductor material. A practicalized example of the resin wiring substrate is configured such that a build-up layer is formed on the front and back surfaces of a core substrate. The core substrate used in the resin wiring substrate is, for example, a resin substrate (glass epoxy substrate) formed by impregnating reinforcement fiber with resin. Through utilization of rigidity of the core substrate, resin insulation layers and conductive layers are alternately laminated on the front and back surfaces of the core substrate, thereby forming respective build-up layers. In the resin wiring substrate, the core substrate serves as a reinforcement and is formed very thick as compared with the build-up layers. The core substrate has conductor lines (specifically, through-hole conductors, etc.) extending therethrough for electrical connection between the build-up layers formed on the front and back surfaces.
In recent years, in association with implementation of high operation speeds of semiconductor integrated circuit devices, high-frequency band signals have been used. In this case, the conductor lines which extend through the core substrate serve as sources of high inductance, leading to a transmission loss of the high-frequency band signals and a circuitry malfunction. Thus, implementation of high operation speed has been hindered. In order to solve this problem, a resin wiring substrate having no core substrate is proposed (refer to, for example, Japanese Patent Application Laid-open (kokai) No. 2002-26171 (FIG. 5, etc.). This substrate does not use a core substrate, which is relatively thick, thereby reducing the overall wiring length. Thus, the transmission loss of the high-frequency band signals is lowered, whereby the semiconductor integrated circuit devices can be operated at high operation speeds.
However, the elimination of a core substrate renders the resin wiring substrate thin, so that a drop in rigidity of the resin wiring substrate is unavoidable. In this case, when solder used for the flip chip connection is cooled, under the influence of thermal stress stemming from a difference in a thermal expansion coefficient of a chip material and a thermal expansion coefficient of a substrate material, the resin wiring substrate is apt to warp toward a side on which the chip is mounted. As a result, cracking is apt to occur in a chip bond zone, so that an open circuit is apt to arise. That is, the formation of a semiconductor package by use of the above-mentioned IC chip results in a failure to achieve high yield and high reliability.
In order to solve the above-mentioned problem, there is proposed a semiconductor package 100 (see FIGS. 18 and 19) configured such that an annular metal stiffener 105 is attached to one side (a substrate main surface 102 or a substrate back surface 103) of a resin wiring substrate 101. The metal stiffener 105 restrains warpage of the resin wiring substrate 101, whereby cracking is unlikely to occur in a bond zone between the resin wiring substrate 101 and an IC chip 106, thereby increasing yield and improving reliability.
However, the metal stiffener 105 is bonded to the substrate main surface 102 of the resin wiring substrate 101 via an adhesive 104. Specifically, the metal stiffener 105 is bonded to the substrate main surface 102 of the resin wiring substrate 101 through solidification of the adhesive 104 effected by heat treatment (curing) at about 150° C. Thus, at the time of cooling after the heat treatment, under the influence of thermal stress stemming from difference in thermal expansion coefficient between a stiffener material and a substrate material, the resin wiring substrate 101 (specifically, its region exposed from an opening portion of the metal stiffener 105) is apt to warp.